M_Jagadeesh97

@Mummanajagadeesh

const char* bio = "No Music, No Work :)";

@rignitc @nitcalicut @mummanajagadeesh 0x0A9FB701319875ED

Followers

Following

Public Repos

Private Repos

Language Breakdown

Lines of code distribution across 47 owned repositories

252.9M Total LOC

Verilog

209,158,060 lines

82.7%

N/A

Python

37,492,710 lines

14.8%

N/A

HTML

2,377,264 lines

0.9%

N/A

Tcl

1,189,152 lines

0.5%

N/A

624,806 lines

0.2%

N/A

Other

2,036,293 lines

0.8%

N/A

I-Shaped Developer

I-shaped

Specialist — deep expertise in Verilog

Verilog

Python

HTML

Tcl

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Coding Streak

Contribution activity over the past year

1 day

1,926

Contributions

834

Commits

Pull Requests

Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun

Based on GitHub activity

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Followers 18

PatStiles

@PatStiles

Noah

@noahwithoutark22

POTINA PAVAN KUMAR

@potinab231172ec-max

RudranandSahu

@RudranandSahu

Ishan.J.Umarjikar

@MANDOXJIN-990

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Following

27 total

Aritra Manna

@aritramanna

dAksh

@DA1729

21verses

@MrRoy09

raulbehl

@raulbehl

Julia Desmazes

@Essenceia

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Synced via GitHub

Top Repositories

line-follower-robot-w

This project features a robot that follows a line using basic sensors. It detects the line on the ground and adjusts its movement to stay on track. The robot can navigate turns and intersections without needing complex algorithms

2 0

Python

fir-accel-caravel-soc

Mixed-signal FIR accelerator SoC on Caravel/Sky130A — CIC decimator, 8-tap programmable FIR filter, PWM DAC, Wishbone CSR

1 0

Verilog

usb-device-controller-core-ip

USB 1.1 Device Controller Core, implemented and verified using self-checking testbenches and automated simulation scripting. The design models the digital protocol layer of a USB device, including packet decoding, control transfer handling, endpoint data management, and protocol state machines; without relying on external PHY or analog modeling

1 0

Verilog

cmos-inverter

CMOS inverter designed in Magic VLSI using SCMOS technology, extracted into a SPICE netlist, and simulated in ngspice. Includes layout, extraction files, and a simulation wrapper with transient analysis and waveform outputs

1 1

PostScript

inverter-rtl-2-gdsii

Complete ASIC design flow for a Simple Inverter — from RTL (Verilog) to GDSII — using the OpenLane toolchain and the SkyWater 130nm PDK (sky130)

1 0

Verilog

hAIck.py_2025

Submission for hAIck.py hackathon hosted by AIML club at NITC, 2025

1 0

Python

aws-deepracer-rl-models

Collection of trained reinforcement learning models for autonomous car racing on AWS DeepRacer. Made it to leaderboards with <1min lap time

1 0

Python

gpbot-w

This 4-wheeled robot is equipped with GPS, IMU, LiDAR, Distance Sensors, and a 2-DOF camera (using linear and rotary actuators). It detects objects using computer vision, avoids obstacles, and navigates autonomously.

1 1

C++

obstacle-avoidance-robot-w

A robot equipped with basic sensors that detects obstacles and changes direction to avoid collisions without using advanced algorithms